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| DATA SHEET MOS INTEGRATED CIRCUIT PD16342 96-BIT AC-PDP DRIVER DESCRIPTION The PD16342 is a high withstand voltage CMOS driver designed for use with a flat display panel such as a PDP, VFD, or EL panel. It consists of a 96-bit bi-directional shift register, 96-bit latch and high withstand voltage CMOS driver. The logic block operates with a 5-V power supply interface (CMOS level input) so that it can be directly connected to a gate array and CPU. The driver block provides a high withstand voltage output: 80 V, +15/-30 mA MAX. The logic and driver blocks are made of CMOS circuits, consuming lower power. FEATURES * Circuit configuration switched by the IBS pin between three 32-bit bi-directional shift registers and six 16-bit bi-directional shift registers. * Data control with transfer clock (external) and latch * High-speed data transfer (fMAX. = 40 MHz MIN. at data latch) (fMAX. = 25 MHz MIN. at cascade connection) * High withstand output voltage (80 V, +15/-30 mA MAX.) * High withstand voltage CMOS structure ORDERING INFORMATION Part Number Package Module/TCP PD16342 Remark Consult an our sales representative regarding the module. Since the module characteristics is based on the module specifications, there may be differences between the contents written in this document and real characteristics. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S15090EJ2V0DS00 (2nd edition) Date Published September 2001 NS CP (K) Printed in Japan The mark # shows major revised points. (c) 2000 PD16342 # 1. BLOCK DIAGRAM (1) (IBS = H, 3-BIT INPUT, 32-BIT LENGTH SHIFT REGISTER) HZ /LBLK /HBLK VDD2 /LE SR1Note A1 CLK R,/L B1 /CLR SR2Note A2 A2 CLK R,/L B2 B2 CLR S95 S2 S5 A1 CLK R,/L B1 CLR S94 S1 S4 S1 S2 S3 LE /L1 O1 VSS2 SR3Note A3 A3 CLK R,/L B3 B3 CLR S96 S94 S95 S96 S3 S6 VDD2 /L96 O96 VSS2 Note SRn: 32-bit shift register Remark /xxx indicates active low signal. 2 Data Sheet S15090EJ2V0DS PD16342 1. BLOCK DIAGRAM (2) (IBS = L, 6-BIT INPUT, 16-BIT LENGTH SHIFT REGISTER) HZ /LBLK /HBLK VDD2 /LE SR1Note A1 S1 S7 CLK R,/L S91 B1 CLR SR2Note A2 S2 S8 CLK R,/L B2 CLR S92 SR3Note A3 S3 S9 CLK R,/L B3 CLR S93 SR4Note A4 S4 S10 CLK R,/L B4 CLR S94 SR5Note A5 S5 S11 CLK R,/L B5 CLR S95 SR6Note A6 S6 S12 CLK R,/L B6 CLR S96 S93 S94 S95 S96 /L96 O96 A1 CLK R,/L B1 /CLR A2 S1 LE S2 /L1 S3 S4 S5 S6 VSS2 O1 B2 A3 B3 A4 B4 A5 B5 A6 VDD2 B6 VSS2 Note SRn: 16-bit shift register Data Sheet S15090EJ2V0DS 3 PD16342 2. PIN FUNCTIONS Symbol /LBLK /HBLK /LE HZ /CLR A1 to A3(6) Pin Name Low blanking High blanking Latch enable Output high impedance Register clear RIGHT data I/O Input Input Input Input Input I/O Note Description /LBLK = L: All output = L /HBLK = L: All output = H Latch on a falling edge H: All output set to the high-impedance state L: All shift register data cleared to the L level R,/L = H, A1 to A3(6): Input, B1 to B3(6): Output The parenthesized pins are used in 6-bit input mode. B1 to B3(6) LEFT data I/O Note R,/L = L, A1 to A3(6): Output, B1 to B3(6): Input The parenthesized pins are used in 6-bit input mode. CLK R,/L Clock Shift control Input Input Shift on a rising edge H: Right shift mode SR1: A1 S1.......S94 B1 (SR2 and SR6 also shift in the same direction.) Left shift mode SR1: B1 S94.......S1 A1 (SR2 and SR6 also shift in the same direction.) IBS Input mode switch Input H: 32-bit shift registers, 3-bit input mode L: 16-bit shift registers, 6-bit input mode O1 to O96 VDD1 VDD2 VSS1 VSS2 High withstand voltage Logic power supply Driver power supply Logic ground Driver ground Output - - - - 80 V, +15/-30 mA MAX. 5 V 5% 15 to 70 V Connect to system ground Connect to system ground Note In 3-bit input mode, unused I/O pins must be held at the L level. To use for module, the back side of IC chip must be held at the VSS (GND) level. 4 Data Sheet S15090EJ2V0DS PD16342 3. TRUTH TABLE Shift Register Block Input R,/L H H L L CLK H or L H or L A Input Output Note2 Output B Output Note1 Shift Register Right shift operation performed Hold Left shift operation performed Hold Output Input Output Notes 1. On the rising edge of the clock, the data of S91 to S93 (S85 to S90) is shifted to S94 to S96 (S91 to S96), and is output from B1 to B3 (B1 to B6) (The parenthesized pins are used in 6-bit input mode.). 2. On the rising edge of the clock, the data of S4 to S6 (S7 to S12) is shifted to S1 to S3 (S1 to S6), and is output from A1 to A3 (A1 to A6) (The parenthesized pins are used in 6-bit input mode.). Latch Block /LE H or L Latch Sn data Hold latch (output) data Output State of Latch Section (/Ln) Driver Block A (B) x x x L H /HBLK L x x H H /LBLK H L x H H HZ L L H L L Output State of Driver Block All driver output: H All driver output: L All driver output: High Impedance L H Remark x: H or L, H: High level, L: Low level Data Sheet S15090EJ2V0DS 5 PD16342 Timing Chart (1) (IBS = H, 3-bit input, right shift) /CLR CLK A1 (B3) A2 (B2) A3 (B1) S1 (S96) S2 (S95) S3 (S94) S4 (S93) S5 (S92) S6 (S91) /LE (Latch on falling edge) /HBLK /LBLK HZ High-impedance O1 (O96) O2 (O95) O3 (O94) O4 (O93) O5 (O92) O6 (O91) Remark Values in parentheses are when R,/L = L. 6 Data Sheet S15090EJ2V0DS PD16342 Timing Chart (2) (IBS = L, 6-bit input, right shift) /CLR CLK A1 (B6) A2 (B5) A3 (B4) A4 (B3) A5 (B2) A6 (B1) S1 (S96) S2 (S95) S3 (S94) S4 (S93) S5 (S92) S6 (S91) S7 (S90) /LE /HBLK /LBLK HZ High-impedance O1 (O96) O2 (O95) O3 (O94) O4 (O93) O5 (O92) O6 (O91) O7 (O90) (Latch on falling edge) Remark Values in parentheses are when R,/L = L. Data Sheet S15090EJ2V0DS 7 PD16342 4. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25C, VSS1 = VSS2 = 0 V) Parameter Logic Supply Voltage Driver Supply Voltage Logic Input Voltage Driver Output Current Operating Junction Temperature Storage Temperature Symbol VDD1 VDD2 VI IO2 TJ Tstg Ratings -0.5 to +6.0 -0.5 to +80 -0.5 to VDD1 + 0.5 +15/-30 +125 -65 to +150 Unit V V V mA C C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Range (TA = -40 to +85C, VSS1 = VSS2 = 0 V) Parameter Logic Supply Voltage Driver Supply Voltage High-Level Input Voltage Low-Level Input Voltage Driver Output Current Symbol VDD1 VDD2 VIH VIL IOH2 IOL2 Conditions MIN. 4.75 15 2.7 0 TYP. 5.0 MAX. 5.25 70 VDD1 0.6 -24 +13 Unit V V V V mA mA 8 Data Sheet S15090EJ2V0DS PD16342 Electrical Characteristics (TA = 25C, VDD1 = 5.0 V, VDD2 = 70 V, VSS1 = VSS2 = 0 V) Parameter High-Level Output Voltage Low-Level Output Voltage High-Level Output Voltage Symbol VOH1 VOL1 VOH21 VOH22 Low-Level Output Voltage VOL21 VOL22 Input Leakage Current High-Level Intput Voltage Low-Level Input Voltage Static Current Dissipation IIL VIH VIL IDD11 Conditions Logic, IOH1 = -1.0 mA Logic, IOL1 = 1.0 mA O1 to O96, IOH2 = -0.52 mA O1 to O96, IOH2 = -5.2 mA O1 to O96, IOL2 = 1.6 mA O1 to O96, IOL2 = 13 mA V1 = VDD1 or VSS1 VDD1 = 4.75 to 5.25 V VDD1 = 4.75 to 5.25 V Logic, TA = -40 to +85C Logic, TA = 25C IDD12 Logic, TA = -40 to +85C Logic, TA = 25C IDD2 Driver, TA = -40 to +85C Driver, TA = 25C 2.7 0 MIN. 0.9 VDD1 0 69 65 1.0 10 1.0 VDD1 0.6 500 300 10 10 Note Note TYP. MAX. VDD1 0.1 VDD1 Unit V V V V V V A V V A A mA mA 1000 100 A A Note When input all input high-level (VIH = 2.7 V to VDD1, but both R,/L and IBS pin are fixed by VI = VSS1 or VDD1) Data Sheet S15090EJ2V0DS 9 PD16342 Switching Characteristics (TA = 25C, VDD1 = 5.0 V, VDD2 = 70 V, VSS1 = VSS2 = 0 V, Logic CL = 15 pF, Driver CL = 50 pF, tr = tf = 6.0 ns) Parameter Propagation Delay Time Symbol tPHL1 tPLH1 tPHL2 tPLH2 tPHL3 tPLH3 tPHL4 tPLH4 tPHZ tPZH tPLZ tPZL Rise Time tTLH tTLZ tTZH Fall Time tTHL tTHZ tTZL Maximum Clock Frequency fMAX. O1 to O96 O1 to O96, RL = 10 k O1 to O96 O1 to O96, RL = 10 k Data latch, duty = 50% Cascade connection, duty = 50% Input Capacitance CI 40 25 15 HZ O1 to O96, RL = 10 k /LBLK O1 to O96 /HBLK O1 to O96 /LE O1 to O96 Conditions CLK A/B MIN. TYP. MAX. 34 34 220 220 205 205 200 200 340 220 340 220 220 3 220 350 3 350 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns s ns ns s ns MHz MHz pF 10 Data Sheet S15090EJ2V0DS PD16342 Timing Requirement (TA = -40 to +85C, VDD1 = 4.75 to 5.25 V, VSS1 = VSS2 = 0 V, tr = tf = 6.0 ns) Parameter Clock Pulse Width Symbol PWCLK(H) PWCLK(L) Latch Enable Pulse Width PW/LE(H) PW/LE(L) Blank Pulse Width HZ Pulse Width /CLR Pulse Width Data Setup Time Data Hold Time Latch Enable Time PW/BLK PWHZ PW/CLR tSETUP tHOLD t/LE1 t/LE2 /CLR Timing t/CLR /HBLK, /LBLK RL = 10 k 600 3.3 12 4 6 12 12 6 ns 12 ns Conditions MIN. 12 TYP. MAX. Unit ns s ns ns ns ns ns ns Data Sheet S15090EJ2V0DS 11 PD16342 # Switching Characteristics Waveform (1/3) 1/fMAX. PWCLK (H) PWCLK (L) 3.3 V 50% CLK 50% 50% VSS1 tSETUP tHOLD An/Bn (Input) 3.3 V 50% 50% VSS1 tPHL1 tPLH1 Bn/An (Output) VOH1 50% 50% VOL1 3.3 V /LE 50% 50% VSS1 PW/LE (H) t/LE1 t/LE2 PW/LE (L) 3.3 V 50% CLK 50% VSS1 tTHL tPHL2 VOH2 10% VOL2 90% On tPLH2 tTLH 90% VOH2 VOL2 On 10% 12 Data Sheet S15090EJ2V0DS PD16342 # Switching Characteristics Waveform (2/3) PW/BLK 3.3 V /LBLK 50% 50% VSS1 tPHL4 tPLH4 90% On 10% VOH2 VOL2 PW/BLK 3.3 V /HBLK 50% 50% VSS1 tPHL3 tPLH3 90% On 10% VOH2 VOL2 PW/CLR 3.3 V 50% /CLR 50% VSS1 t/CLR 3.3 V CLK 50% VSS1 Clock rising edge for valid data Data Sheet S15090EJ2V0DS 13 PD16342 # Switching Characteristics Waveform (3/3) PWHZ 3.3 V HZ 50% 50% VSS1 tPLZ tTLZ tPZL tTZL VO (H) 90% On 10% 90% 10% VOL2 VOH2 90% 90% On 10% tPHZ tTHZ 10% tPZH tTZH VO (L) 14 Data Sheet S15090EJ2V0DS PD16342 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S15090EJ2V0DS 15 |
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